1. Technical Field
Embodiments of the present disclosure generally relate to semiconductor devices and more particularly to semiconductor devices including a normal test signal generator and termination signal generator.
2. Related Art
Semiconductor devices may be designed and fabricated to include a test mode function for evaluating the operation thereof. That is, various parameters of the semiconductor devices may be measured in a test mode at a wafer level or at a package level and the tested semiconductor devices may be sorted into good chips or failed chips according to the test results. Further, each of the semiconductor devices may include various test modes. For example, each of the semiconductor devices may include a normal test mode for evaluating a normal circuit used in input/output (I/O) of data and an extra test mode for evaluating circuits other than the normal circuit.
The semiconductor device may receive a plurality of address signals supplied from an external device to activate a test mode relating to a combination of the address signals and may be tested if the test mode is activated. A test operation in the test mode may be executed by information stored in a mode register set (MRS) and by decoding the plurality of address signals supplied from the external device. Thus, the semiconductor device may be designed to include a decoder that decodes the plurality of address signals.